As physical circuit densities on Very Large Scale Integrated (VLSI) chips increase and the performance (clock frequencies) increases, the signal integrity of on chip electrical nets becomes a major design consideration. The signal integrity of the on chip nets is a function of the electrical noise margin of the receiver circuits and the magnitude of the electrical noise affecting the nets. A source of electrical noise is the transient fluctuations of the local power supply voltages caused by the switching of circuits. The magnitude of this noise is a function of the number of simultaneous switching devices, their sizes, load capacitance, physical positions and densities on the chip, as well as the electrical characteristics of the power supply distribution.
A design technique employed to manage this transient power supply noise is to place decoupling capacitance on the power supply locally to where the sources (switching devices causing the noise) are located. These capacitors dampen the high frequency noise on the power supply distribution. Unfortunately, in typical applications the required amount of decoupling capacitance is unknown or estimated. Thus, if excess capacitance is used, valuable chip area is wasted, if insufficient capacitance is used, generated high frequency noise remains unabated. Therefore, there is a need in the art for a method for evaluating the amount of decoupling capacitance in a given area or within a given area of a noise source and determining if the decoupling capacitance employed is sufficient.